A pipelined architecture with novel memory structure is proposed with several modifications of the ME algorithm. Fast motion estimation with low hardware cost and less memory access is achieved by proper search strategy, efficient rate distortion optimization (RDO) cost calculation and interpolation components, innovative memory structure and optimized dataflow scheduling. The proposed design is synthesized by SMIC 130 nm CMOS technology process with a clock frequency of 167 MHz and consumes 181.7 K logic gates and 13.8 KB memory, which shows great hardware efficiency compared with other designs. The proposed design was finally integrated within an H.264/AVC encoder for FPGA prototyping and VLSI implementation. The core area of the overall chip is 1.74 mm×1.74 mm with SMIC 65 nm CMOS technology which can support real-time HD(1080P@60fps) encoding with a clock frequency of 350 MHz.

Base on traditional integrated circuit (IC) low power methods, the authors propose three low power technologies for further research and take an implementation of WSN sensor node as an example. At system level, the authors present an optimum scheme combined with compiling technology and a hardware structure which provides special low power modes for WSN. At circuit level, considering clock placement in arithmetic mapping phase, clock operators in collaboration with IC operator design methodology (ODM) is proposed. A low power design of WSN sensor node is implemented to verify the low power technologies presented above. The testing results show that WSN sensor node consumes 167 μW at chip level and PCB system 1.035 mW at PCB system level in deep sleep mode by the three methods.

With a verification environment based on the UVM (universal verification Methodology) verification methodology and UVM1.1 standard library, building a reference model through the aspect-oriented paradigm and separation of properties of function, timing and structure and generating the high functional coverage test cases based on knowledge base at the transaction level, the integrated verification platform took the PKU-DSPII as example, to implement RISC CPU-oriented functional verification and domain reuse. Experimental results show that the reusability is enhanced significantly and the coverage efficiency of the test cases improves about 7% relatively.

By analyzing the application demand of the medical electronics, an MCU architecture named PKU-DSPII with application specific instruction set is proposed. Multilevel storage structures with direct memory access controller (DMAC) and abundant system control modules and peripheral interfaces are integrated in the MCU, which supports three booting modes including self-updating mode. PKU-DSPII is implemented with CSMC 0.18μm technology and LQFP package while the die area is 3.2 mm×3.2 mm and the measured power consumption is 96.9 mW at working frequency of 100 MHz.

In order to make on-line topic detection more efficient, a new method is proposed based on named entity recognition. New method extracts news elements from stories. Based on news elements, query composition is used to detect story link. This process reduces complex computation of text similarities. Experimental result indicates that the proposed method performs on-link topic detection accurately and efficiently.

Even XML is used as a popular data exchange standard over Internet and Intranet, its space expansion makes the transmitting and storing of XML data very expensive in terms of resources because of adding tags to every different semantic content unit. After compressed, its size will be much smaller, but how to evaluate query efficiently and directly based on the compressed data is still a necessary work. The authors propose an XML index structure using B+ tree as its' backbone structure, on compressed data which is resulted from revert arithmetic compression, ArithRegion. Queries as the form of //element₁/element₂/…/elment_m can be evaluated efficiently using ArithRegion.

Mining moving sequential patterns has great significance for effective and efficient location management in wireless communication systems. Mining moving sequential patterns is different from mining conventional sequential patterns, firstly it needs to consider much about the time factor in moving sequences; secondly it cares about what the next moving is for mobile user, so items must be successive in mining moving sequential patterns. A novel technique to mine moving sequential patterns is proposed. A clustering method is introduced to preprocess the original moving histories into moving sequences, whose main role is to discretize the time attribute. And then an efficient method, called PrefixTree, is presented to mine the moving sequences. Performance study shows that PrefixTree outperforms Revised PrefixSpan-2, which is revised to mine moving sequences, in mining large moving sequence databases.